1. Field of the Invention
The present invention relates to a display driving circuit for driving a fluorescent display tube, liquid crystal display or the like, and in particular relates to a technique for suppressing peak currents in display driving circuits having a blanking control function.
2. Description of the Related Art
FIG. 2 is a configuration of a conventional driver circuit disclosed in Japanese Patent Kokai No. 5-110266.
This driver circuit drives the lighting of LEDs (Light-Emitting Diodes), fluorescent display tubes or the like. The driver circuit includes a four-bit shift register 1, four-bit data latch 2, four AND (logical product) gates 3, a FF (Flip-Flop) 4, and output terminals Q0 to Q3. The shift register 1 receives a data signal DATA as serial input in synchronization with a clock signal CLK, and then the shift register 1 converts the data into parallel data so that the parallel data are output as four-bit output signals. The data latch 2 captures and outputs the four-bit output signals supplied from the shift register 1 when a latch signal LAT is at “H” level, and continuously outputs the captured signals without modification, even though the latch signal LAT becomes “L” level.
The FF 4 receives a blanking signal BLK in synchronization with the clock signal CLK, and outputs the signal as a control signal CON. The four AND gates 3 respectively calculate the logical products of the four-bit signals output from the data latch 2 and the control signal CON, and output the calculation results from the output terminals Q0 to Q3.
In this driver circuit, the serially-input data signal DATA is captured by the shift register 1 on the rising edge of the clock signal CLK, and is output in parallel from all the bits of the shift register 1. The signals output from the shift register 1 are latched by the data latch 2 during an interval in which the latch signal LAT is “H”, and then the signals are supplied to the AND gates 3. On the other hand, the blanking signal BLK is supplied to control output from this driver circuit. The blanking signal BLK, which changes at an arbitrary time independent from the clock signal CLK, is converted at the FF 4 into a control signal CON in synchronization with the clock signal CLK.
When the control signal CON is “L”, the AND gates 3 are in the off state, and therefore the output signals from the output terminals Q0 to Q3 are always “L”. When the control signal CON is “H”, the AND gates 3 are in the on state, and therefore the output signals from the data latch 2 are transmitted to the output terminals Q0 to Q3 through the AND gates 3.
Since the control signal CON is changed in synchronization with the clock signal CLK, change of the output signals from the output terminals Q0 to Q3 is delayed from the timing of the clock signal CLK for a period of time corresponding to the circuit. Accordingly, switching currents flow during the transient state to change the output signals from the output terminals Q0 to Q3, so that even though noise occurs in the signal lines, this noise and the timing of the clock signal CLK do not overlap. Accordingly, it becomes possible to prevent the erroneous operations due to switching current upon changing of the output signals, and to prevent capturing erroneous data signals DATA in the shift register 1 at the rising edge of the clock signal CLK.
In the above-described driver circuit, the output signals of the output terminals Q0 to Q3 are changed simultaneously in response to the change of the control signal CON. Consequently, when the load of the LED, fluorescent display tube or the like connected to the output terminals Q0 to Q3 is large, the switching currents through the load circuits are superposed, so that a peak current from a power supply source during switching becomes extremely large, causing a temporary reduction of the power supply voltage. As a result, there is a possibility of erroneous operation.